1. Field of the Invention
The present invention relates, generally, to a system for monitoring bit errors and, more particularly, to a system for monitoring bit errors in digital differential phase modulation communications. The bit errors are mainly generated in transmission lines and the probability of their generation is usually extremely small, for example, on the order of less than 10.sup.-3 or 10.sup.-4.
2. The Prior Art
Generally, differential phase modulation is used in digital communications. Such modulation is advantageous in that an absolute reference phase is unnecessary for demodulating a modulated signal, transmitted from a transmitter, in a receiver. In differential phase modulation information is represented by changes in carrier phase. The changes are responsive to relative changes between two successive bits in a pulse train. In digital differential phase modulation communications, bit errors may be generated due to failures of the components, failures in transmission lines and so on. Therefore, it is necessary to have a system for monitoring such bit errors.
One prior art system for monitoring bit errors in digital communications comprises a parity counter in each side of a transmitter and a receiver. The parity counter is used to count all the pulses in a pulse train whose length is a definite interval (hereinafter referred to as a frame) and to produce a parity bit whose value is "1" or "0", depending on whether the counted result is odd or even. In this system, a pulse in a pulse train represents a value "1". In the transmitter, the parity counter counts the number of pulses in the pulse train and the counted result is inserted as a first parity bit into the pulse train. Next, the pulse train, including the first parity bit, is transmitted from the transmitter to the receiver. In the receiver, the parity counter counts the number of pulses in the pulse train and produces the counted result as a second parity bit. Next, the second parity bit is compared with the transmitted first parity bit. As a result, when these parity bits are different from each other, a signal indicating the detection of bit errors is generated.
However, when the above-mentioned system is applied to digital differential phase modulation communications, bit errors can not be detected. Thus, the number of pulses in a pulse train is not changed and, accordingly, the parity bit, representing whether the number of pulses is odd or even, is not changed. This is because the bit representation of a transmitted signal in such digital communications is determined by a change relative to a preceding bit and, accordingly, one bit error causes another bit error, that is, bit errors are generated in pairs.